<p><em>Educational Engineering Team · Weekly Engineering Challenge · Launch Oct 22, 2026 · Deadline Oct 29, 2026, 23:59 Africa/Cairo (UTC+3)</em></p>
<h2>The hook</h2>
<p>You wire a sensor to an ADC, open the serial plotter, and the signal is buried under a fat, steady wobble: 50 Hz (60 Hz in the Americas) picked up from the mains wiring around you. A plain moving average smears your real signal along with the hum. This week you build a filter that cuts out <em>one</em> frequency like a scalpel. <strong>Before:</strong> a noisy, wobbling trace. <strong>After:</strong> the same signal, clean, with a measured attenuation number to prove it.</p>
<h2>What students will learn</h2>
<ol>
<li>Sampling theory in practice: fixed sample rate, Nyquist, aliasing, and why you need an anti-alias filter.</li>
<li>How a second-order IIR (biquad) notch works: poles, zeros, Q, and bandwidth.</li>
<li>Turning a formula into firmware: Direct Form I difference equation, state variables, fixed vs. floating point.</li>
<li>Timer-driven real-time sampling and measuring timing jitter.</li>
<li>Measuring a filter: attenuation in dB, pass-band gain, and step/settling behavior.</li>
</ol>
<h2>Real-world use</h2>
<p>Mains interference is a classic problem in low-level measurement: strain gauges and load cells, audio, and biopotential instruments. That's why many instruments include a power-line notch or line-synchronous rejection. The same biquad structure is the building block of audio equalizers. <em>(This challenge uses a safe synthetic test signal only. It is NOT a medical device project. Never connect anything to the human body or to mains.)</em></p>
<h2>Engineering theory explained</h2>
<p><strong>Terms.</strong></p>
<ul>
<li><em>Sample rate Fs</em>: how many ADC readings per second. It must be constant, because every coefficient assumes it.</li>
<li><em>Nyquist frequency</em>: Fs/2. Content above it <em>aliases</em>: it folds back and shows up as a fake lower frequency.</li>
<li><em>Notch filter</em>: a band-stop filter with a very narrow stop band.</li>
<li><em>Q (quality factor)</em>: center frequency ÷ −3 dB bandwidth. Higher Q gives a narrower notch.</li>
<li><em>dB</em>: gain_dB = 20·log10(Vout/Vin). −20 dB means the amplitude is divided by 10; −40 dB means it is divided by 100.</li>
</ul>
<p><strong>Principle.</strong> A biquad has two zeros and two poles. A notch places its zeros exactly on the unit circle at ±ω0. That gives (theoretically) zero gain at f0. The poles sit just inside the circle at the same angle, so the response recovers to ~1 right next to the notch. The closer the poles are to the circle, the higher the Q and the narrower the notch.</p>
<p><strong>Design equations</strong> (RBJ Audio EQ Cookbook, W3C Note):</p>
<ul>
<li>ω0 = 2π·f0/Fs, α = sin(ω0)/(2Q)</li>
<li>b0 = 1, b1 = −2cos ω0, b2 = 1; a0 = 1+α, a1 = −2cos ω0, a2 = 1−α (normalize everything by a0)</li>
<li>Difference equation (Direct Form I): y[n] = (b0x[n] + b1x[n−1] + b2x[n−2] − a1y[n−1] − a2y[n−2]) / a0</li>
</ul>
<p><strong>Calculated (theory only, not measured)</strong> for Fs = 1000 Hz, f0 = 50 Hz, Q = 10, double precision:</p>
<table>
<thead>
<tr>
<th>f (Hz)</th>
<th>5</th>
<th>20</th>
<th>40</th>
<th>45</th>
<th>48</th>
<th>50</th>
<th>52</th>
<th>55</th>
<th>60</th>
<th>100</th>
</tr>
</thead>
<tbody>
<tr>
<td>Gain (dB)</td>
<td>0.00</td>
<td>−0.01</td>
<td>−0.20</td>
<td>−0.86</td>
<td>−3.9</td>
<td>ideal null</td>
<td>−4.1</td>
<td>−1.02</td>
<td>−0.30</td>
<td>−0.02</td>
</tr>
</tbody>
</table>
<p>Normalized coefficients: b = [0.98478, −1.87317, 0.98478], a = [1, −1.87317, 0.96957]. Real hardware will <strong>not</strong> reach the "ideal null". ADC noise, coefficient quantization, sample-rate error, and the real mains frequency drifting a little around nominal all limit the depth. Finding that limit is part of the challenge.</p>
<p><strong>Trade-offs.</strong></p>
<ul>
<li>High Q gives a narrow notch that preserves nearby signal, but it rings longer and is sensitive to frequency mismatch. Low Q is more robust but eats more nearby signal.</li>
<li>Float vs. fixed point (Q15/Q31): fixed point is faster on small MCUs, but the poles sit close to the unit circle, so coefficient rounding can move the notch or make the filter unstable.</li>
<li>Notch vs. alternatives: moving average (crude), FIR band-stop (linear phase but many taps), adaptive notch (tracks drift but is more complex).</li>
</ul>
<p><strong>Likely failure modes.</strong> Sample rate not actually constant (e.g., sampling in <code>loop()</code> with <code>delay()</code>). Aliasing from a missing anti-alias RC. Integer overflow in the state. Coefficients computed for the wrong Fs. Forgetting the ADC DC offset. A notch set to 50 Hz in a 60 Hz country.</p>
<h2>System architecture</h2>
<pre><code>[Test-signal source]  wanted 5 Hz sine  +  &quot;hum&quot; 50 Hz sine  (summing resistor network or PC sound card / 2nd MCU PWM+RC)
        │  (0–3.3 V, biased to mid-rail, NEVER mains-connected)
        ▼
[Anti-alias RC low-pass]  fc well below Fs/2
        ▼
[MCU ADC]  ◄── [Hardware timer ISR @ fixed Fs]  (measure jitter on a GPIO toggle)
        ▼
[Biquad notch, Direct Form I]  (float or Q15/Q31)
        ▼
[Output]  UART/serial plot of raw vs filtered (and/or DAC/PWM out to a scope)
        ▼
[Measurement]  amplitude at 5 Hz &amp; 50 Hz before/after → dB
</code></pre>
<p>Diagram: see the cover image (explanatory illustration).</p>
<h2>Bill of materials / software</h2>
<table>
<thead>
<tr>
<th>Item</th>
<th>Qty</th>
<th>Role</th>
<th>Notes / substitutes</th>
</tr>
</thead>
<tbody>
<tr>
<td>Any MCU board with a 10–12-bit ADC and hardware timer</td>
<td>1</td>
<td>Sampling + filtering</td>
<td>STM32 "Blue/Black Pill", Raspberry Pi Pico (RP2040), Arduino Uno/Nano, Teensy. ESP32 is fine but deliberately not required</td>
</tr>
<tr>
<td>Signal source</td>
<td>1</td>
<td>Generates wanted + hum test signal</td>
<td>Function generator, PC/phone sound-card tone app via an AC-coupled, biased input, or a second MCU making two PWM tones through RC filters</td>
</tr>
<tr>
<td>Resistors 10 kΩ (several), capacitors 100 nF–1 µF</td>
<td>few</td>
<td>Summing, mid-rail bias, anti-alias RC</td>
<td>Any values that meet your calculated fc</td>
</tr>
<tr>
<td>Breadboard + jumpers</td>
<td>1</td>
<td>Prototyping</td>
<td></td>
</tr>
<tr>
<td>Optional: oscilloscope / logic analyzer</td>
<td>1</td>
<td>Jitter and output verification</td>
<td>Cheap USB logic analyzer + PulseView is enough for timing</td>
</tr>
<tr>
<td>Software</td>
<td></td>
<td></td>
<td>Arduino IDE / PlatformIO / STM32CubeIDE / Pico SDK; Python + NumPy/SciPy (<code>scipy.signal.iirnotch</code>, <code>freqz</code>) for design and verification; Wokwi or any simulator for the beginner path</td>
</tr>
</tbody>
</table>
<p>Prices are intentionally not quoted (not verified). <strong>Safety:</strong> low-voltage only (≤ 5 V). Never derive the hum from the mains, never probe mains wiring, and keep the ADC input within its rated range. Sound-card outputs need AC coupling plus a bias network and an amplitude check before connecting to an ADC.</p>
<h2>Guided process</h2>
<ol>
<li><strong>Pick Fs and f0.</strong> Start with Fs = 1000 Hz and f0 = your local mains frequency. Justify why Fs ≥ ~10× f0 makes life easier.</li>
<li><strong>Design offline first.</strong> Compute coefficients by hand from the equations, then check them against <code>scipy.signal.iirnotch(f0, Q, fs)</code>. Plot <code>freqz</code>. Do not move on until the two agree.</li>
<li><strong>Build the test signal.</strong> Mix a 5 Hz "wanted" tone and a 50 Hz "hum" tone into one ADC input, biased to mid-rail. Record their individual amplitudes.</li>
<li><strong>Anti-alias.</strong> Choose an RC so that content near and above Fs/2 is attenuated. Show your fc calculation (fc = 1/(2πRC)).</li>
<li><strong>Timer-driven sampling.</strong> Start the ADC from a hardware timer interrupt (or timer-triggered ADC/DMA). Toggle a GPIO every sample and measure the period and jitter. Avoid <code>delay()</code>-based loops.</li>
<li><strong>Firmware modules.</strong> (a) sampler ISR → ring buffer, (b) <code>biquad_process(state*, x)</code> returning y, (c) logger streaming <code>raw,filtered</code> over serial. Pseudocode:
   <code>on_timer_isr():  x = adc_read() - dc_offset ; push(x)
   main_loop():     while buffer not empty: x = pop(); y = biquad(&amp;s, x); print(x, y)
   biquad(s, x):    y = b0*x + b1*s.x1 + b2*s.x2 - a1*s.y1 - a2*s.y2 ; shift state ; return y</code>
   You decide the details: float vs fixed point, scaling, buffer size.</li>
<li><strong>Measure.</strong> Feed hum only, then wanted only, then both. Compute amplitudes (peak-to-peak or RMS over whole cycles, or an FFT in Python on logged data) and report dB.</li>
<li><strong>Debug.</strong> If the notch is shallow, check Fs accuracy first, then coefficient precision, then the real hum frequency.</li>
</ol>
<h2>The challenge mission</h2>
<p>Build (or simulate) a real-time 50/60 Hz notch filter on a microcontroller and <strong>prove with measurements</strong> that it removes the hum while preserving a low-frequency wanted signal.</p>
<p><strong>Minimum functional requirements</strong></p>
<ol>
<li>A fixed sample rate driven by a hardware timer (or a timer-triggered ADC), with measured period and jitter reported.</li>
<li>A second-order IIR notch at your local mains frequency, with coefficients derived from the equations and cross-checked in software (e.g., SciPy).</li>
<li>A safe, low-voltage test signal containing a wanted component (≤ 10 Hz) and a hum component (50 or 60 Hz).</li>
<li>A logged raw vs. filtered output (serial plot, CSV, or scope capture).</li>
<li>Measured attenuation at the hum frequency and measured gain change at the wanted frequency, both in dB.</li>
<li>A written explanation of your chosen Q and Fs.</li>
</ol>
<p><strong>Constraints</strong></p>
<ul>
<li>One biquad section (second order) for the core notch, so you can compare designs fairly.</li>
<li>The filter must run sample-by-sample in real time; no offline post-processing for the main result.</li>
<li>Per-sample processing time must be measured and must fit inside one sample period.</li>
<li>Low-voltage only; no mains-derived signals.</li>
</ul>
<h2>Acceptance tests</h2>
<table>
<thead>
<tr>
<th>#</th>
<th>Input condition</th>
<th>Measure</th>
<th>Evidence</th>
<th>Pass if</th>
</tr>
</thead>
<tbody>
<tr>
<td>T1 Timing</td>
<td>Timer running at the chosen Fs</td>
<td>Sample period and jitter (GPIO toggle on scope/logic analyzer, or timer timestamps)</td>
<td>Screenshot or log</td>
<td>Mean period within ±1 % of 1/Fs, and the method is shown</td>
</tr>
<tr>
<td>T2 Hum rejection</td>
<td>Hum tone only, at mains frequency</td>
<td>Output vs input amplitude</td>
<td>Before/after plot + numbers</td>
<td>Attenuation ≥ 20 dB measured</td>
</tr>
<tr>
<td>T3 Signal preservation</td>
<td>Wanted tone only (≤ 10 Hz)</td>
<td>Output vs input amplitude</td>
<td>Plot + numbers</td>
<td>Gain change within ±1 dB</td>
</tr>
<tr>
<td>T4 Combined</td>
<td>Wanted + hum together</td>
<td>Visual + numeric</td>
<td>Raw vs filtered trace</td>
<td>Hum visibly removed; T2/T3 numbers hold within your stated tolerance</td>
</tr>
<tr>
<td>T5 Budget</td>
<td>Normal operation</td>
<td>Per-sample processing time</td>
<td>Timer/cycle counter or GPIO pulse width</td>
<td>Less than one sample period</td>
</tr>
</tbody>
</table>
<p><strong>Definition of success:</strong> T1–T3 pass with real measured numbers (or real simulation output on the simulation path), plus a T4 trace. Untested claims are scored as not passed.</p>
<h2>Beginner pathway</h2>
<p>Simulation only. In Python (or a spreadsheet), generate 2 s of a 5 Hz sine plus a 50 Hz sine at Fs = 1000 Hz. Implement the difference equation in a plain loop (not <code>lfilter</code>). Plot before/after and compute the amplitude at both frequencies. Same concept, no hardware.</p>
<h2>Standard pathway</h2>
<p>The full hardware build described in sections 6–10 on any MCU, with T1–T5.</p>
<h2>Advanced extensions</h2>
<ol>
<li><strong>Fixed point:</strong> port to Q15/Q31, then compare notch depth and CPU time against float. Watch stability.</li>
<li><strong>Frequency mismatch study:</strong> sweep the hum between 49 and 51 Hz and plot notch depth vs. mismatch for Q = 5, 10, and 30.</li>
<li><strong>Harmonics:</strong> cascade notches at 50/100/150 Hz and report the extra CPU cost and pass-band impact.</li>
<li><strong>Adaptive notch:</strong> track the real hum frequency (e.g., an LMS adaptive filter with a reference) and compare it with the fixed notch.</li>
<li><strong>Transient behavior:</strong> apply a step to the input and measure ringing/settling time vs. Q.</li>
</ol>
<h2>Troubleshooting and common mistakes</h2>
<ul>
<li><strong>Notch shallow or off-center:</strong> print the measured Fs. If it's 980 Hz instead of 1000 Hz, your notch moved. Recompute or fix the timer.</li>
<li><strong>Output explodes or saturates:</strong> check the a1/a2 signs (the difference equation subtracts them) and integer overflow in the state. Try float first.</li>
<li><strong>Ghost frequencies:</strong> that's aliasing. Check the anti-alias RC and that the hum amplitude stays inside the ADC range.</li>
<li><strong>Huge DC on the output:</strong> subtract the mid-rail bias, or accept that a notch passes DC (it should) and plot accordingly.</li>
<li><strong>Serial plotter freezes:</strong> printing every sample at a high baud can starve the loop. Decimate the logging, not the filter.</li>
<li><strong>Wanted signal shrinks:</strong> your Q is too low, or the wanted frequency is too close to f0.</li>
</ul>
<h2>Submission instructions and deadline</h2>
<p><strong>Deadline: Thursday Oct 29, 2026, 23:59 Africa/Cairo (UTC+3).</strong>
Submit by replying under the challenge post at <strong>https://academy.eduengteam.com/community/educational-engineering-community-3125/</strong>. Paste the template below and add links to a public repo, simulation, or images. If the platform doesn't allow attachments, link to a public host (GitHub, Gist, Wokwi, Google Drive "anyone with link") instead. Only share what you're comfortable making public; no personal contact details needed. First attempts and partial builds are welcome.</p>
<h2>Discussion starters</h2>
<ol>
<li>Q = 5 or Q = 30 for a mains notch? Which fails first when the grid frequency drifts, and why?</li>
<li>Is a fixed-point biquad worth it on a 32-bit MCU with an FPU? What did your CPU-time numbers say?</li>
<li>Notch vs. a sample rate that's an exact multiple of the mains frequency plus averaging over whole cycles: when does each win?</li>
<li>Direct Form I vs. Transposed Direct Form II: which behaves better in fixed point, and how would you show it?</li>
<li>Would you rather remove hum in analog (twin-T) or digital? Defend your choice with cost and tolerance.</li>
</ol>
<h2>References / accuracy note</h2>
<ul>
<li>W3C Working Group Note, <em>Audio EQ Cookbook</em> (adapted from R. Bristow-Johnson): biquad notch formulas. https://www.w3.org/TR/audio-eq-cookbook/</li>
<li>SciPy documentation, <code>scipy.signal.iirnotch</code>: notch design, Q = w0/bw. https://docs.scipy.org/doc/scipy/reference/generated/scipy.signal.iirnotch.html</li>
<li>Texas Instruments, J. Karki, <em>Active Low-Pass Filter Design</em> (SLOA049): anti-alias filter background. https://www.ti.com/lit/an/sloa049b/sloa049b.pdf</li>
</ul>
<p><strong>Accuracy note:</strong> the gain table in section 5 is <em>calculated</em> from the ideal equations (double precision). No hardware was built for this post, and no measured results are claimed. The ≥ 20 dB / ±1 dB thresholds are challenge pass criteria, not reported performance.</p>
<hr />
<h2>Interaction pieces (handoff section 5)</h2>
<p><strong>Prediction question (before you build):</strong> The grid isn't exactly 50.000 Hz. If your Q = 30 notch is centered at 50.0 Hz and the hum is really at 50.3 Hz, will you still get 20 dB of rejection? Write down your guess and your reasoning <em>before</em> you test it.</p>
<p><strong>Design-choice poll:</strong> <em>Float or fixed-point biquad?</em>
A) Float: simple and numerically safe, but slower on MCUs without an FPU.
B) Q15/Q31 fixed point: fast and deterministic, but at risk of coefficient rounding and overflow.
Vote in the comments and say which MCU you're using.</p>
<p><strong>Checkpoint 1 (architecture):</strong> Post your block diagram or schematic, your chosen Fs, Q, and anti-alias fc, and your hand-computed coefficients vs. SciPy's.</p>
<p><strong>Checkpoint 2 (prototype):</strong> Post a raw vs. filtered serial plot, a simulation screenshot, a code fragment of your biquad, or a 15–60 s clip.</p>
<p><strong>Final submission template</strong></p>
<pre><code>Name/handle (optional):
Project version: Beginner / Standard / Advanced / Simulation
Hardware/software used:
Design summary:
Repository or circuit/simulation link (if public):
Demo photo or 15–60 s video:
Test inputs, measured outputs, and pass/fail:
Biggest problem and how I debugged it:
One improvement I would make:
</code></pre>
<p><strong>Review rubric</strong> (scored only with adequate evidence): Functional success and measurable tests 35% · Engineering explanation and technical accuracy 25% · Design process, debugging, and iteration 25% · Documentation and communication 15%. No prizes or certificates are offered.</p>
<p>Canonical post: https://eduengteam.substack.com/p/weekly-engineering-challenge-can</p>

Build a real-time 50/60 Hz biquad notch filter on a microcontroller and prove with measurements that it removes mains hum while preserving your signal.

Weekly Engineering Challenge: Can You Build a Digital Filter That Deletes Mains Hum Without Erasing Your Signal?

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Weekly Engineering Challenge: Can You Build a Digital Filter That Deletes Mains Hum Without Erasing Your Signal?

Weekly Engineering Challenge: Can You Build a Digital Filter That Deletes Mains Hum Without Erasing Your Signal?

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